The present invention relates to a transistor circuit and, particularly, to a level converter circuit for receiving and converting a signal from a circuit operating on a first power voltage into a signal for another circuit operating on a second power voltage.
Increase of power consumption of an integrated circuit is considerable due to recent increase in integration density of integrated circuits and increase of operating frequency thereof. In order to restrict the increase of power consumption, reduction of power source voltage has been studied. In considering the reduction of power source voltage, there may be two cases, one in which a low voltage power sources of, for example, 3 V for operating an internal circuit of a device and a high voltage power source of, for example, 5 V for operating an input/output portion of the device as in a conventional integrated circuit are used and the other in which integrated circuits which operate with power source voltages of 3 V and 5 V, respectively, are arranged mixedly within a single device.
In either of these two cases, it is necessary to convert a signal having an amplitude of 3 V into a signal having an amplitude of 5 V. That is, a transistor circuit for a purpose of level conversion is needed. For example, in the former case, a conversion from 3 V to 5 V is required in an interface portion between the internal circuit operating with 3 V and the input/output portion operating with 5 V and, in the latter case, such conversion is required in an input circuit portion of an integrated circuit of 5 V for receiving a signal output from an integrated circuit of 3 V thereof.
When a CMOS inverter circuit is used for such a signal level conversion, however, both a P channel MOS transistor and an N channel MOS transistor which constitute the CMOS inverter circuit are turned on in a period during which an input signal is in a high level and therefore a DC current flows, resulting in an increase of power consumption.
A first example of a conventional level conversion circuit using a CMOS inverter circuit will be described in detail with reference to FIG. 5.
In FIG. 5, an output terminal of a circuit portion connected to a terminal V1 of a low source voltage (e.g. 3 V) constituted with a P channel MOS transistor (referred to as PMOS, hereinafter) 108 and an N channel MOS transistor (referred to as NMOS, hereinafter) 109 is connected to an input terminal I of a circuit portion which is connected to a terminal V2 of a high source voltage (e.g., 5 V).
An input circuit of the high source voltage portion is constituted with a first inverter circuit composed of a PMOS 103 and an NMOS 104 having input terminals connected to an input terminal I of the input circuit and a second inverter circuit composed of a PMOS 105 and an NMOS 106 and supplied with an output of the first inverter circuit as an input. An output of the second inverter circuit is connected to an output terminal O of the input circuit.
In FIG. 5, when the PMOS 108 and the NMOS 109 on the low source voltage side are turned OFF and ON, respectively, and a signal potential at the input terminal I is changed from high level to low level, that is, from a potential of the low voltage source terminal V1 to a ground potential, the PMOS 103 and the NMOS 104 of the first inverter circuit on the high voltage source side are turned ON and OFF, completely. Therefore, its output achieves a potential of the high voltage source terminal V2. The PMOS 105 and the NMOS 106 of the second inverter circuit respond to this potential to turn OFF and ON, respectively. Thus, the potential at the output terminal O achieves a low level, that is, ground potential, causing no problem to occur.
However, when the PMOS 108 and the NMOS 109 on the low voltage source side are turned ON and OFF, respectively, and the signal potential at the input terminal I is changed from a low level to a high level, that is, from the ground potential to the potential of the low voltage source terminal V1, the NMOS 104 of the first inverter circuit on the high voltage source side is turned ON.
Since, in this case, the PMOS 103 of the first inverter circuit is supplied at its gate with the potential of the low voltage source terminal V1 and at its source with the potential of the high voltage source terminal V2, a voltage V1-V2 is applied between the gate and the source. When this voltage between the gate and the source is lower in a negative direction than a threshold voltage (negative value) of the PMOS 103, that is, when the voltage is larger in absolute value than the threshold value, the PMOS 103 is turned ON, so that a current path is formed from the high voltage source terminal V2 through the PMOS 103 and the NMOS 104 to the ground terminal, through which a current flows constantly. This current is also referred to as "through-current".
Assuming that, for example, the voltage of the low voltage source terminal V1 is 3 V and the voltage of the high voltage source terminal V2 is 5 V, a voltage of -2 V is applied between the gate and the source of the PMOS 103. Since the threshold voltage V.sub.TP of the usual PMOS 103 is in the order of -0.8 V, the PMOS 103 becomes fully ON.
By setting an ON resistance of the NMOS 104 to a value considerably smaller than an ON resistance of the PMOS 103, it is possible to make the output of the first inverter circuit as low as the ground potential regardless of the fact that both the PMOS 103 and the NMOS 104 are in ON state. In this case, the PMOS 105 and the NMOS 106 of the second inverter circuit are turned ON and OFF, respectively, and the signal level at the output terminal O becomes high level, that is, the potential of the high voltage source terminal V2.
As mentioned above, in the circuit construction shown in FIG. 5 which uses the CMOS inverter circuits, the required level conversion is possible. However, since, when the potential at the input terminal I is in a high level, the PMOS 103 of the first inverter circuit is not turned OFF, a current path is formed from the high voltage source terminal through the PMOS 103 and the NMOS 104 to the ground terminal. Therefore, for an integrated circuit including a number of the level conversion circuits each shown in FIG. 5, power consumption is increased.
In order to solve the problems of the level conversion circuit shown in FIG. 5, a level conversion circuit shown in FIG. 6 has been proposed.
The level conversion circuit shown in FIG. 6 includes, in addition to the elements constructing the level conversion circuit shown in FIG. 5, an enhancement NMOS 501 having a drain connected to the input terminal I, a gate connected to the high voltage source terminal V2 and a source connected to the input of the first inverter circuit composed of the PMOS 103 and the NMOS 104 and a PMOS 102 having a drain connected to the input of the first inverter circuit, a gate connected to the output of the first inverter circuit and a source connected to the high voltage source terminal V2.
In FIG. 6, when the PMOS 108 and the NMOS 109 are turned OFF and ON, respectively, and the potential at the input terminal I changes from the potential level of the low voltage source terminal V1 to the ground potential, the NMOS 501 is turned ON. Therefore, the input potential of the first inverter circuit composed of the PMOS 103 and the NMOS 104 is reduced and thus the output potential of the first inverter circuit is increased, so that the PMOS 102 and the NMOS 106 constituting the second inverter circuit are turned OFF and ON, respectively. Therefore, the output terminal O thereof achieves a low level, that is, the ground potential.
On the contrary, when the PMOS 108 and the NMOS 109 are turned ON and OFF, respectively, and the potential at the input terminal I increases from the ground potential to the potential level of the low voltage source terminal V1, the input of the first inverter circuit composed of the PMOS 103 and the NMOS 104 becomes high level since the NMOS 501 is initially in ON state. Therefore, the NMOS 104 is turned ON and the output of the first inverter circuit becomes low level to turn the PMOS 102 ON.
With the PMOS 103 being turned ON, the potential at the input of the first inverter circuit is pulled up to the potential level of the high voltage source terminal V2, so that the PMOS 103 is fully turned OFF. Simultaneously, the output of the second inverter circuit composed of the PMOS 105 and the NMOS 106 is inverted and the output terminal O is pulled up to the potential level of the high voltage source terminal V2.
As mentioned above, in the level converter circuit shown in FIG. 6, since, when the input terminal I is at the potential of the low voltage source terminal V1, the gate potential of the PMOS 103 of the first inverter circuit is pulled up to the potential level of the high voltage source terminal V2 through the PMOS 102, the PMOS 103 is fully turned OFF and, therefore, the current path which is formed in the conventional circuit shown in FIG. 5 through the PMOS 103 and the NMOS 104 is not formed.
However, in the level converter circuit shown in FIG. 6, there is another problem that, when a difference in voltage between the low voltage source terminal V1 and the high voltage source terminal V2 is large, a current path is formed from the high voltage source terminal V2 through the PMOS 102, the NMOS 501 and PMOS 108 to the low voltage source terminal V1.
That is, in order to turn the NMOS 501 OFF when the input terminal I is in high level, the voltage difference V2-V1 must be smaller than the threshold voltage VTN of the NMOS 501. An amount of current flowing from the high voltage source terminal V2 to the low voltage source terminal V1 when the above condition is not satisfied, that is, V2-V1.gtoreq.VTN, is smaller than that of the current flowing through the PMOS 103 and the NMOS 104 of the conventional circuit shown in FIG. 5. However, when the number of level converter circuits used in an integrated circuit is large, power consumption therein is still large.
As a modification of the level conversion circuit shown in FIG. 6, the gate electrode of the NMOS 501 may be connected to not the high voltage source terminal V2 but to the low voltage source terminal V1. As another modification, an intermediate voltage between the voltage of the low voltage source terminal V1 and the voltage of the high voltage source terminal V2 is generated suitably and applied to the gate electrode of the NMOS 501.
In the former modification, however, the high level voltage at the input of the first inverter circuit composed of the PMOS 103 and the NMOS 104, that is, the output voltage of the NMOS 501, is the potential V1 of the low voltage source terminal V1 reduced by the threshold voltage VTN of the NMOS 501. Therefore, if V1 is low, the potential at the input of the first inverter circuit becomes short, that is, too low, causing the first inverter circuit to be inoperable.
In the latter modification, when the intermediate voltage is closer to the potential at the high voltage source terminal V2, the same current path as that formed in the level conversion circuit shown in FIG. 6 is formed from the high voltage source terminal V2 to the low voltage source terminal V1 and, when the intermediate voltage is closer to the potential at the low voltage source terminal V1, the first inverter circuit becomes inoperable. Therefore, the setting range of the intermediate voltage value is narrow, causing the design thereof to be not easy.
FIG. 7 shows another conventional level conversion circuit which is proposed in Japanese Patent Application Laid-open No. H2-134918 to improve the problems of the level conversion circuit shown in FIG. 6. The level conversion circuit shown in FIG. 7 differs from the level conversion circuit shown in FIG. 6 in that the NMOS 501 in FIG. 6 is replaced by a depletion type NMOS 601 having a gate electrode connected to the output of the first inverter circuit composed of the NMOS 103 and the NMOS 104.
In FIG. 7, when the potential at the input terminal I changes from the potential level of the low voltage source terminal V1 to the ground potential level, that is, at a leading edge of the potential, the depletion NMOS 601 becomes in ON state and thus the input and the output of the first inverter circuit composed of the PMOS 103 and the NMOS 104 are changed to low level and high level, respectively. Therefore, the PMOS 102 is turned OFF and the depletion NMOS 601 is ONed deeper, so that the input of the first inverter circuit is lowered to the ground potential. Consequently, the output terminal O of the second inverter circuit composed of the PMOS 105 and the NMOS 106 is changed from high level to low level.
On the contrary, when the potential at the input terminal I changes from the ground potential level to the potential of the low voltage source terminal V1, that is, at the leading edge of the potential, the depletion NMOS 601 achieves an OFF state since the gate electrode of the depletion NMOS 601 is applied with the voltage of the high voltage source terminal V2 and the PMOS 102 becomes in ON state. Thus, the input of the first inverter circuit is changed to the potential level of the low voltage source terminal V1 and the output thereof is changed to low level.
Then, the depletion NMOS 601 having the gate electrode supplied with the output voltage of the first inverter circuit is changed to the OFF state. Further, since the PMOS 102 is turned ON, the input potential of the first inverter circuit is changed from the potential of the low voltage source terminal V1 to the potential of the high voltage source terminal V2, so that it is possible to completely turn the PMOS 103 of the first inverter circuit OFF. Since the input of the second inverter circuit is changed from the potential of the high voltage source terminal V2 to the ground potential, the output terminal O of the second inverter circuit is changed from the ground potential level to the potential level of the high voltage source terminal V2.
In the level conversion circuit shown in FIG. 7, when the potential of the input terminal I is the potential of the low voltage source terminal V1, the current path through the PMOS 103 and the NMOS 104 are cut by the presence of the PMOS 102. Further, NMOS 601, cuts the current path from the high voltage source and the low voltage source because the gate potential thereof is set to the ground potential.
In order to make the lower limit of the threshold voltage VTN of the NMOS 601 -V1 and to discharge the input of the first inverter circuit by the NMOS 601 having the gate grounded, the upper limit of the threshold voltage VTN must be at least smaller than 0 V. Therefore, in the level conversion circuit shown in FIG. 7, the NMOS 601 must be of the depletion type.
In the level conversion circuit shown in FIG. 7, an increase in power consumption due to formation of extra current paths is prevented as mentioned above. However, when such circuit is mounted on a CMOS integrated circuit, its fabrication becomes complicated and expensive due to the use of the depletion type NMOS.